DocumentCode
3304327
Title
A 7 mask CMOS-technology utilizing liquid phase selective oxide deposition
Author
Kanba, K. ; Horiuchi, T. ; Homma, T. ; Murao, Y. ; Okumura, K.
Author_Institution
NEC Corp., Kanagawa, Japan
fYear
1991
fDate
8-11 Dec. 1991
Firstpage
637
Lastpage
640
Abstract
The authors describe a fully symmetric 7 mask CMOS technology, utilizing a room-temperature liquid phase oxide deposition technique which has selectivity against photo resist. They have developed process modules for self-aligned well and one mask LDD (lightly doped drain) formation which achieve excellent device performance. The main features of this CMOS technology are (1) very short processing time: (7 masks to first metallization); (2) self-aligned twin retrograde wells with 40% reduction of p/sup +/-n/sup +/ spacing; and (3) optimal LDD design using different-width side-wall spacers for n- and p-channel MOSFETs with a 10% larger on current for p-channel MOSFETs.<>
Keywords
CMOS integrated circuits; integrated circuit technology; oxidation; 7 mask technology; CMOS technology; device performance; features; liquid phase selective oxide deposition; one mask LDD; optimal LDD design; room temperature processing; room-temperature liquid phase oxide deposition; selectivity against photo resist; self-aligned well; short processing time; side-wall spacers; spacing reduction; twin retrograde wells; CMOS process; CMOS technology; Chemical technology; Hot carrier effects; Implants; Impurities; MOSFETs; Resists; Space technology; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location
Washington, DC, USA
ISSN
0163-1918
Print_ISBN
0-7803-0243-5
Type
conf
DOI
10.1109/IEDM.1991.235391
Filename
235391
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