PWM switching patterns optimization for multilevel inverter using a FPGA

This paper presents the implementation on a field programmable gate array (FPGA) of a PWM switching patterns optimization for a voltage multilevel inverter. FPGA is used for generating of the switching patterns and dead time for a cascaded multilevel inverter. The design uses a PWM sinusoidal in order to have a control signal to generate the signals remaining. These signals are developed by delays applied to control signal. Useful advantages of this scheme are the easy implementation of software control and flexibility in adaptation to generate many output voltage levels. Simulations and experimental results are included.