DocumentCode
3304688
Title
Low temperature CMOS self-aligned poly-Si TFTs and circuit scheme utilizing new ion doping and masking technique
Author
Inoue, S. ; Matsuo, M. ; Hashizume, T. ; Ishiguro, H. ; Nakazawa, T. ; Ohshima, H.
Author_Institution
Seiko Epson Corp., Nagano, Japan
fYear
1991
fDate
8-11 Dec. 1991
Firstpage
555
Lastpage
558
Abstract
Low-temperature (>
Keywords
CMOS integrated circuits; ion implantation; liquid crystal displays; logic gates; oscillators; shift registers; thin film transistors; 110 keV; 300 mm; 600 degC; CMOS; CMOS circuits; active matrix LCDs; circuit scheme; high accelerating voltage; integrated drivers; inverters; ion doping technique; ion implantation; large beam area; large glass substrates; liquid crystal displays; low temperature processing; masking technique; polycrystalline Si; polysilicon self-aligned TFTs; ring oscillators; self-aligned structure; shift registers; thin-film transistors; CMOS process; CMOS technology; Doping; Driver circuits; Glass; Liquid crystal displays; Particle beams; Substrates; Temperature; Thin film transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location
Washington, DC, USA
ISSN
0163-1918
Print_ISBN
0-7803-0243-5
Type
conf
DOI
10.1109/IEDM.1991.235409
Filename
235409
Link To Document