A 0.35 mu m CMOS process for fast random logic

Advanced high-performance CMOS circuits with 0.35 mu m gate length were developed using mixed e-beam/optical lithography. These circuits have been processed with the following features: field isolation with a SILO/RTN (sealed interface local oxidation by rapid thermal nitridation) process, n+ polysilicon gate, TaSi/sub 2/ gate material, contact with W plug and RTA for both BPSG reflow and junction activation. These modules have been applied to point out speed performances of 0.35 mu m CMOS demonstrator circuits. A 2.8 V power supply voltage was adopted to satisfy the trade-off between circuit performance and reliability. A gate delay of 52 ps/stage and a 16*16 bit multiplication time of 5.2 ns were measured. Due to careful device optimization, good device behavior with high drivability, no leakage current in weak inversion characteristics, and negligible short channel effects were observed.<>