3.3 V BiNMOS technology using NPN transistors without buried layers

Author

Shida, A. ; Kagamihara, M. ; Komatsu, M. ; Kumagai, K. ; Hirata, M.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1991

fDate

8-11 Dec. 1991

Firstpage

93

Lastpage

96

Abstract

A VLSI technology suitable for low-voltage BiNMOS logic has been developed. A BiNMOS device structure, N substrate based emitter-followed CMOS (NECMOS), is proposed. NECMOS has a simple structure using a substrate NPN (S-NPN) transistor which does not need buried layers. This use of an N substrate and a thin epitaxial layer is capable of realizing low collector resistance for S-NPN. A polysilicon emitter type S-NPN transistor, with a maximum cutoff frequency of 9 GHz, has been integrated into a 0.8 mu m CMOS structure with three additional masks. The fan-out coefficient of the propagation delay time for a BiNMOS 2-NAND gate is 1/2.4 of that for a CMOS 2-NAND gate under 3.3 V operation.<>

Keywords

BIMOS integrated circuits; VLSI; integrated circuit technology; 0.8 micron; 2-NAND gate; 3.3 V; 9 GHz; BiNMOS technology; LV logic; N substrate; NECMOS; NPN transistors; VLSI technology; emitter-followed CMOS; maximum cutoff frequency; n-p-n transistors; polysilicon emitter; thin epitaxial layer; BiCMOS integrated circuits; Boron; CMOS logic circuits; Epitaxial layers; Impurities; Large scale integration; Logic devices; National electric code; Substrates; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0243-5

Type

conf

DOI

10.1109/IEDM.1991.235416

Filename

235416