Title :
A method for measuring 3D stress distributions inside a silicon chip
Author :
Sutor, Alexander ; Lerch, Reinhard
Author_Institution :
Dept. of Sensor Technol., Friedrich Alexander Univ., Erlangen
fDate :
Oct. 30 2005-Nov. 3 2005
Abstract :
In this paper, a method for the measurement of 3D stress distributions in silicon chips is presented for the first time. It is based on an electrical impedance tomography (EIT) technique. This technique allows the detection of resistivity distributions inside a body by measuring signals on the surface. Due to the piezoresistive effect, which is very large in semiconductors, the distribution of stress can be calculated with a certain resolution depending on the number and location of surface contacts. For the three dimensional EIT technique, substrate contacts are arranged on the surface in a regular pattern. The depth, which the current through the substrate reaches, depends on the distance of the contacts. Therefore, the stress situation in different layers of the chip can be separated
Keywords :
electric impedance imaging; elemental semiconductors; silicon; stress measurement; 3D stress distribution measurement; Si; chip layers; electrical impedance tomography; pattern surface; piezoresistive effect; resistivity distribution detection; silicon chip; substrate contact; surface contact location; surface contact number; Conductivity; Piezoresistance; Semiconductor device measurement; Signal resolution; Silicon; Stress measurement; Substrates; Surface impedance; Time measurement; Tomography;
Conference_Titel :
Sensors, 2005 IEEE
Conference_Location :
Irvine, CA
Print_ISBN :
0-7803-9056-3
DOI :
10.1109/ICSENS.2005.1597870
