Title :
High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation
Author :
Kesan, V.P. ; Subbana, S. ; Restle, P.J. ; Tejwani, M.J. ; Aitken, J.M. ; Iyer, S.S. ; Ott, J.A.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Quarter-micron Si/sub 1-x/Ge/sub x/ p-MOS devices with either thermal or PECVD oxides have been fabricated using an integrable process module (LOCOS isolation, threshold and deep well implants, p/sup +/ polysilicon gates, and TiSi/sub 2/) compatible with conventional 0.25 mu m CMOS with the Si/sub 1-x/Ge/sub x/ channel and Si cap deposited by selective UHV-CVD. Improvements in mobility and transconductance over deep submicron (0.25 mu m channel length) state-of-the-art Si p-MOSFETs were demonstrated by using silicon-germanium channels with low (10-25%) germanium content, both at room temperature (300 K) and low temperature (82 K). The use of Si/sub 1-x/Ge/sub x/ channels can provide better device performance in the same technology generation (same lithography, junction depth, etc.) and also help compensate for the external parasitic resistance penalty.<>
Keywords :
CMOS integrated circuits; Ge-Si alloys; carrier mobility; insulated gate field effect transistors; integrated circuit technology; semiconductor materials; 0.25 micron; 300 K; 77 K; 82 K; CMOS compatible; LOCOS; PECVD oxides; PMOS device; Si cap; Si/sub 1-x/Ge/sub x/ channel; SiGe-Si; TiSi/sub 2/; deep well implants; integrable process module; mobility; p-MOSFETs; p/sup +/ polysilicon gates; quarter micron devices; selective UHV-CVD; thermal oxides; transconductance; CMOS process; CMOS technology; Epitaxial layers; Germanium silicon alloys; Implants; MOS devices; MOSFET circuits; Silicon germanium; Temperature; Transconductance;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235432
