Floating-body problems and benefits in fully depleted SOI CMOS VLSI circuits

A physical model for the fully depleted submicron SOI (silicon-on-insulator) MOSFET is described and used to assess problems and possible benefits in SOI CMOS VLSI digital circuits that result from the parasitic bipolar junction transistor (BJT) in the floating-body device. It is shown that the problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by device/circuit simulations. The physical model for the fully depleted SOI MOSFET described here has been written into SPICE2 source code.<>