A novel cell structure for 4 M bit full feature EEPROM and beyond

Author

Ajika, N. ; Ohi, M. ; Futatsuya, T. ; Arima, H. ; Matsukawa, T. ; Tsubouchi, N.

Author_Institution

Mitsubishi Electric Corp., Hyogo, Japan

fYear

1991

fDate

8-11 Dec. 1991

Firstpage

295

Lastpage

298

Abstract

A novel EEPROM cell structure is proposed, which realizes a small cell size of 9.72 mu m/sup 2/ by using 0.8- mu m minimum feature size. The cell fabricated has sufficient cell threshold windows which extend to more than 5 V and program cell current of more than 80 mu A at a nominal program voltage of 12 V. The cell endurance is more than 10/sup 4/ erase/write cycles. A 4 Mb full-feature EEPROM can be acquired using this cell structure. The full-feature EEPROM cell has neither disturb nor overerasure problems, which are very difficult obstacles for flash EEPROM development, and can be operated by single and low-voltage external power supply.<>

Keywords

CMOS integrated circuits; EPROM; VLSI; integrated memory circuits; 0.8 micron; 12 V; 4 Mbit; 5 V; 80 muA; CMOS process; EEPROM; ULSI; cell endurance; cell size; cell structure; cell threshold windows; erase/write cycles; feature size; flash EEPROM; full-feature EEPROM cell; low-voltage external power supply; program cell current; program voltage; single voltage supply; CMOS technology; Costs; EPROM; Fabrication; Isolation technology; Large scale integration; Lithography; Nonvolatile memory; Space technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0243-5

Type

conf

DOI

10.1109/IEDM.1991.235445

Filename

235445