Sort Optimization Algorithm of Median Filtering Based on FPGA

The traditional sorting algorithm of median filtering is optimized according to the hardware structure features of FPGA. FPGA is used to acquire the data parallelly for comparing the data of the same column in the median filtering window. Comparing results shared by adjacent filter window are saved temporarily to match the new round of median filtering by using FPGA internal resources. This method can reduce the comparing times from current 21 down to 13, and improve the algorithm efficiency nearly 40%.The experimental results prove that the optimized algorithm can filter a 1K×1K gray-level image in about 20ms, which ensure the proposed algorithm can be applied in the real-time image median filtering system.