Title :
Logic testing of CMOS structures
Author_Institution :
Dept. of Informatics, Szechenyi Univ., Gyor
Abstract :
The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck short (short circuit) behavior. In this paper only combinational logic circuits are taken into consideration. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program
Keywords :
CMOS logic circuits; combinational circuits; fault diagnosis; logic testing; CMOS digital circuits; CMOS structures; combinational logic circuits; line-value justification; logic testing; multiple faults; open circuit; short circuit; single fault; switch-level logic faults; test calculation principle; transistor faults; CMOS digital integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Digital circuits; Joining processes; Logic testing; Semiconductor device modeling; Switches; Switching circuits;
Conference_Titel :
Computational Cybernetics, 2004. ICCC 2004. Second IEEE International Conference on
Conference_Location :
Vienna
Print_ISBN :
0-7803-8588-8
DOI :
10.1109/ICCCYB.2004.1437668
