Author_Institution :
Vitesse Semiconductor, Camarillo, CA, USA
Abstract :
The author presents an overview of ion-implanted GaAs MESFET device fabrication, and the interconnect and process technologies developed for GaAs VLSI circuits. Circuit topologies and circuit results for GaAs VLSI are also presented. It is noted that the development and improvement of self-aligned refractory gate MESFET process technology, which produces high-quality enhancement and depletion transistors, allows the use of simple, high performance DCFL (direct coupled FET logic) circuit topology. This circuit family, coupled with advanced, high density, low capacitance interconnect technology provides the capability for very-high-performance, low-power GaAs VLSI circuits. Silicon MOS processing techniques and equipment have been used for fabrication of the circuits, and silicon-like circuit topologies, design tools, and design techniques have been used to design, verify, and test the circuits. Circuits of 100000 gate complexity are currently available.<>
Keywords :
III-V semiconductors; Schottky gate field effect transistors; VLSI; digital integrated circuits; direct coupled FET logic; field effect integrated circuits; gallium arsenide; ion implantation; logic arrays; DCFL; GaAs; MESFET process technology; VLSI circuits; depletion transistors; direct coupled FET logic; enhancement transistors; fabrication; gate arrays; gate complexity 100000; low capacitance interconnect technology; self-aligned refractory gate; semiconductors; silicon-like circuit topologies; Circuit testing; Circuit topology; Coupling circuits; FETs; Fabrication; Gallium arsenide; Integrated circuit interconnections; MESFET circuits; Transistors; Very large scale integration;
