Title :
SOI device structures implementing 650 V high voltage output devices on VLSIs
Author :
Yasuhara, N. ; Nakagawa, A. ; Furukawa, K.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
It has been experimentally verified that 650 V breakdown voltage can be realized in lateral devices on a 14- mu m-thick SOI (silicon on insulator). The device structure is characterized by a shallow N-type diffusion layer on a 3- mu m-thick bottom oxide film. Trenches will be available for device isolation by using a thin SOI film for a power IC. The combination of high-voltage thin SOI device structures and the trench isolation technique will make VLSIs with high-voltage output devices possible.<>
Keywords :
BIMOS integrated circuits; VLSI; insulated gate bipolar transistors; integrated circuit technology; power integrated circuits; power transistors; semiconductor-insulator boundaries; wafer bonding; 14 micron; 3 micron; 650 V; SOI device structures; Si-SiO/sub 2/; VLSIs; breakdown voltage; device isolation; high voltage output devices; lateral devices; power IC; shallow N-type diffusion layer; silicon direct bonding; thin SOI film; trench isolation technique; Breakdown voltage; Cathodes; Dielectrics; Diodes; Isolation technology; Power integrated circuits; Silicon compounds; Thickness measurement; Very large scale integration; Wafer bonding;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235481
