DocumentCode :
3306845
Title :
Effect of current levels on memory behaviour of MNOS structures — Limits of computer simulation
Author :
Horvath, Zs J. ; Molnar, K.Z.
Author_Institution :
Inst. of Microelectron. & Technol., Obuda Univ., Budapest, Hungary
fYear :
2013
fDate :
8-10 July 2013
Firstpage :
303
Lastpage :
307
Abstract :
MNOS memory hysteresis and memory window are simulated by calculation of tunneling probability via the potential barrier to the nitride conductance or valence band, or to Si nanocrystals embedded in the dielectric layers. The effect of the oxide and nitride current levels are studied. The memory hysteresis width depends strongly on the oxide current level. If the oxide current is close to the nitride current, the flat-band voltage shift is low. If the oxide current is lower than the nitride current, the hysteresis curve changes its direction. The nitride current level affects the hysteresis height only due to charge loss via the nitride layer. At very high oxide currents the memory behaviour collapses, but it is obtained by the simulation of memory hysteresis only, it does not appear in the simulation of memory window.
Keywords :
MIS structures; dielectric hysteresis; electric admittance; field effect transistors; probability; tunnelling; MNOS memory hysteresis; MNOS structures; computer simulation; dielectric layers; flat-band voltage shift; hysteresis curve; hysteresis height; memory FET; memory behaviour; memory capacitor; memory hysteresis width; memory window; nitride conductance; nitride current levels; nitride layer; oxide current levels; tunneling probability; valence band; Computer simulation; Field effect transistors; Hysteresis; Nanocrystals; Silicon; Threshold voltage; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Cybernetics (ICCC), 2013 IEEE 9th International Conference on
Conference_Location :
Tihany
Print_ISBN :
978-1-4799-0060-2
Type :
conf
DOI :
10.1109/ICCCyb.2013.6617608
Filename :
6617608
Link To Document :
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