DocumentCode
3307092
Title
Completely verifying memory consistency of test program executions
Author
Manovit, Chaiyasit ; Hangal, Sudheendra
Author_Institution
Stanford Univ., CA, USA
fYear
2006
fDate
11-15 Feb. 2006
Firstpage
166
Lastpage
175
Abstract
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intentional data races are placed in a test program, there may be many correct results according to the memory consistency model supported by the system. For popular memory models like SC and TSO, the problem of verifying correctness of an execution is known to be NP-complete. As a result, analysis techniques implemented in the past have been incomplete: violations of the memory model are flagged if provable, otherwise the result is inconclusive and it is assumed optimistically that the machine´s results are correct. In this paper, we describe for the first time a practical, new algorithm which can solve this problem with certainty, thus ensuring that incorrect behavior of a large, complex multiprocessor cannot escape. We present results of our analysis algorithm on test programs run on a newly designed multiprocessor system built by Sun Microsystems. We show that our algorithm performs very well, typically analyzing a program with 512 K memory operations distributed across 60 processors within a few minutes. Our algorithm runs in less than 2.6 times the time taken by an incomplete baseline algorithm which may miss errors. Our approach greatly increases the confidence in the correctness of the results generated by the multiprocessor, and allows us to potentially uncover more bugs in the design than was previously possible.
Keywords
microprogramming; parallel architectures; performance evaluation; shared memory systems; NP-complete; Sun Microsystems; commercial-grade shared memory multiprocessor; data race; memory consistency verification; pseudo-random test program execution; Algorithm design and analysis; Computer bugs; Lamps; Multiprocessing systems; Performance analysis; Software testing; Spine; Sun; System testing; Vehicle crash testing;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 2006. The Twelfth International Symposium on
ISSN
1530-0897
Print_ISBN
0-7803-9368-6
Type
conf
DOI
10.1109/HPCA.2006.1598123
Filename
1598123
Link To Document