A reconfigurable high level FPGA-based coprocessor

FPGA technology enjoys both the high performance of a dedicated hardware solution and the flexibility of software that is offered by its inherent reprogrammability feature. Image processing is one application area that can benefit greatly from FPGAs performance and flexibility. This paper presents the design and implementation of a high-level reconfigurable image coprocessor on FPGAs. The image coprocessor high level instruction set is based on the operators of image algebra. Central to this Instruction set are the five core neighbourhood operations of image algebra: convolution, additive maximum, additive minimum, multiplicative maximum and multiplicative minimum. These are parameterised in terms of the neighbourhood operation´s window coefficients, window size and image size. Handel-C language was used to design the image coprocessor with a fully tested prototype on Celoxica Virtex-E based RC1000-PP PCI board. The paper describes the user´s programming interface, and outlines the approach to generating FPGA architectures dynamically for the image coprocessor. It also presents sample implementation results (speed, area) for different neighbourhood operations