Direct measurement and analysis of the time-dependent evolution of stress in silicon devices and solder interconnections in power assemblies

One key failure mechanism in power assemblies involves degradation of solder joints. This failure mechanism is governed by the mechanical stress induced within the devices, solder interconnections and substrates as a result of their differing coefficients of thermal expansion. Furthermore, this stress is determined by the architecture of the interconnections. Finally, it is suspected that extreme mechanical stress can lead to deviations in the operational characteristics of the semiconductor devices. Therefore, a complete understanding is required of the nature of stress evolution during packaging, and its time and temperature dependence during service. Previously, measurement of this stress has been restricted. However, we report on the application of a new piezospectroscopic methodology for quantitatively measuring the mechanical stress in silicon devices with extremely high spatial and stress resolution; typically, measurement accuracies of /spl plusmn/15 MPa and 1 /spl mu/m are achieved. An experimental test matrix has been constructed of specimens comprising silicon test devices attached directly to copper substrates with a range of solder alloys, and silicon die sizes. The distributions of stress within the devices are measured and analyzed according to analytical shear lag models from which the in situ physical properties of solder alloys are deduced. Finally the implications on package reliability are discussed.