A New High-Speed Architecture for Reed-Solomon Decoder

This paper proposes a new VLSI architecture for decoding Reed-Solomon codes with a modified Berlekamp-Massey algorithm. By employing t-folded architecture, we achieve the highest throughput and the resource utilization efficiency without degrading performance on critical path delay. More interestingly, on the basis of the proposed architecture, further complexity benefit can be realized by sharing hardware units among sub-blocks, which is usually neglected in previous research. Two algorithms using this sharing technique are given and demonstrated to reduce the hardware complexity dramatically. Compared to the current commercial IP core, the proposed architectures are more advantageous in a certain content of the characteristics.