InP MISFETs with SiO/sub 2/ gate insulator deposited by distributed electron cyclotron resonance plasma deposition

The authors report on the fabrication of enhancement-mode InP MISFETs in which the gate dielectric was SiO/sub 2/, deposited by distributed electron cyclotron resonance plasma enhanced chemical vapor deposition (DECR-PECVD) directly on the semi-insulating InP wafer. Sources and drains were formed by ion implantation and annealing. In this process, use was made of a new and very efficient method based on the epitaxial growth of a thick InGaAs layer which acts as an implantation mask and as an encapsulating cap of the channel area during the high-temperature postimplantation annealing. Long channel (L/sub g/=3 to 8 mu m) MISFETs processed with these two new techniques show a high transconductance (intrinsic transconductance g/sub m/=60 mS/mm for L/sub g/=3 mu m) and a relatively small drain current drift (7.8% between 0.08 and 5000 s at V/sub g/=1 V and V/sub d/=0.2 V).<>