Debug facilities in the TriMedia CPU64 architecture

Author

Vranken, Harald

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1999

fDate

25-28 May 1999

Firstpage

76

Lastpage

81

Abstract

This paper describes debug facilities in the Philips TriMedia CPU64, which is an embedded processor core for multimedia applications. Its architecture provides a VLIW pipeline, support for 64-bit vector data, and virtual memory management. The debug hardware in the TriMedia CPU64 supports two complementary debug strategies. One strategy provides a snapshot of the processor state at certain moments in time, which is achieved by single-step execution and various breakpoint types. The other debug strategy provides continuous monitoring of the processor state by using a PC trace buffer. Precise exceptions are used to provide accurate context switching from application software to debugger software.

Keywords

computer debugging; embedded systems; integrated circuit testing; microprocessor chips; multimedia computing; parallel architectures; 64 bit; PC trace buffer; Philips TriMedia CPU64; TriMedia CPU64 architecture; VLIW pipeline; application software; continuous monitoring; debug hardware; embedded processor core; multimedia applications; single-step execution; virtual memory management; Application software; Coprocessors; Debugging; Hardware; Identity-based encryption; Laboratories; Silicon; Software tools; Streaming media; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Workshop 1999. Proceedings

Conference_Location

Constance, Germany

Print_ISBN

0-7695-0390-X

Type

conf

DOI

10.1109/ETW.1999.804255

Filename

804255