Leakage Current Reduction in 6T Single Cell SRAM at 90nm Technology

The emerging Wireless Sensor Network technologies are facilitating novel applications in health monitoring, industrial monitoring and security surveillance. The small physical dimensions of wireless sensor nodes often restrict the energy source to a small battery. The limited energy consumption requirement demands for ultra-low power sensing, processing and communication. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. The popular approaches for leakage reduction are the data retention gated ground, and dynamic threshold voltage for cache. The work focuses on the simulation of a SRAM Cell for the data retention gated ground and drowsy mode SRAM Cell which shows that the current reduction of around 25% in s simulation model, respectively in comparison with the conventional cell with no current reduction technique.