Energy-Aware Network-on-Chip Architecture Using Perfect Difference Network

Network-on-Chip (NoCs) are currently viewed as a revolutionary approach to provide a scalable, high performance and robust infrastructure for on-chip communication. Network-on-Chip (NoCs) interconnection architecture to be used in System-on-Chip (SoCs) meet the communication requirements of these systems, offering at the same time, reusability, scalability and parallelism in communication. Furthermore, they cope with other issues like energy constraint and clock distribution. Energy consumption of Network-on-Chip architecture becomes one of the most vital parameter to optimize in the most of the system design. Therefore it is essential to develop energy-aware techniques for Network-on-Chip architecture. In this paper, we discuss the energy-aware Network-on-Chip architecture based on the mathematical notion of Perfect Difference Sets (PDS). In this paper, we propose the energy model for Network-on-Chip architecture using Perfect Difference Network (PDN). In this paper, we are proposing energy-aware model for PDN Circular geometry and PDN Inter-link geometry of Network-on-Chip architecture. The proposed energy model is then validated against simulation results obtained with PDN Inter-link geometry and PDN circular geometry for Network-on-Chip (NoC) architecture. The simulation results shows that significant energy saving is achieved for PDN Inter-link geometry in comparison with PDN circular geometry on the basis of our proposed energy model.