• DocumentCode
    3310361
  • Title

    An efficient VLSI architecture for H.264 subpixel interpolation coprocessor

  • Author

    Dang, Philip P.

  • Author_Institution
    STMicroelectronics Inc., San Diego, CA, USA
  • fYear
    2006
  • fDate
    7-11 Jan. 2006
  • Firstpage
    87
  • Lastpage
    88
  • Abstract
    This paper presents an efficient VLSI architecture to implement subpixel interpolation for H.264 video compression standard.
  • Keywords
    VLSI; coprocessors; data compression; image resolution; video coding; H.264 video compression standard; VLSI architecture; subpixel interpolation coprocessor; Computational complexity; Computer architecture; Coprocessors; Costs; Equations; Finite impulse response filter; Interpolation; Motion compensation; Tree data structures; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics, 2006. ICCE '06. 2006 Digest of Technical Papers. International Conference on
  • Print_ISBN
    0-7803-9459-3
  • Type

    conf

  • DOI
    10.1109/ICCE.2006.1598323
  • Filename
    1598323
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3310361