Title :
An efficient VLSI architecture for H.264 subpixel interpolation coprocessor
Author_Institution :
STMicroelectronics Inc., San Diego, CA, USA
Abstract :
This paper presents an efficient VLSI architecture to implement subpixel interpolation for H.264 video compression standard.
Keywords :
VLSI; coprocessors; data compression; image resolution; video coding; H.264 video compression standard; VLSI architecture; subpixel interpolation coprocessor; Computational complexity; Computer architecture; Coprocessors; Costs; Equations; Finite impulse response filter; Interpolation; Motion compensation; Tree data structures; Very large scale integration;
Conference_Titel :
Consumer Electronics, 2006. ICCE '06. 2006 Digest of Technical Papers. International Conference on
Print_ISBN :
0-7803-9459-3
DOI :
10.1109/ICCE.2006.1598323
