Title :
Reconfigurable data path processor: implementation and application for signal processing algorithms
Author :
Chavan, Ameet ; Nava, Patricia A. ; Moya, Jphn A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., El Paso, TX, USA
Abstract :
The paper briefly describes reconfigurable architecture classifications and comparisons, as well as an FPGA implementation of a simplified version of the reconfigurable data path processor (RDPP) using Xilinx design tools. The FPGA configured as RDPP can be employed for a wide variety of signal processing applications. That is, the inherent parallel nature of the architecture lends itself to signal processing algorithms, which are discussed. Simulations of operations on the input data stream, which include multiply-and-accumulate (MAC) operations used in filters and matrix manipulation for image processing applications, are presented.
Keywords :
field programmable gate arrays; integrated circuit design; logic design; matrix algebra; parallel architectures; reconfigurable architectures; signal processing; FPGA; Xilinx design tools; filters; image processing; input data stream; matrix manipulation; multiply-and-accumulate operations; parallel architecture; reconfigurable architecture classifications; reconfigurable data path processor; signal processing algorithms; Circuit testing; Computer applications; Computer architecture; Field programmable gate arrays; Hardware; Programmable logic devices; Reconfigurable architectures; Reconfigurable logic; Signal processing algorithms; Software design;
Conference_Titel :
Digital Signal Processing Workshop, 2004 and the 3rd IEEE Signal Processing Education Workshop. 2004 IEEE 11th
Print_ISBN :
0-7803-8434-2
DOI :
10.1109/DSPWS.2004.1437938
