Signal Latency Evaluation and Signal Synchronization for Electrically and Optically Linked Interconnections

Author

Muslim, Shirazy Md Shorab ; Lee, Tae-Woo ; Park, Hyo-Hoon

Author_Institution

Inf. & Commun. Univ., Daejeon

Volume

3

fYear

2008

fDate

17-20 Feb. 2008

Firstpage

2161

Lastpage

2165

Abstract

Signal latency between optical and electrical interconnections is modeled and evaluated. As interconnection length is increased latency is also increased and signals become asynchronous. To compensate this latency, a signal synchronizing block which can synchronize the asynchronous signal according to clock signal is proposed and designed in this paper. This synchronizing block is consists of D flip-flop, voltage control delay cell (VCDC) and designed by a commercial 0.13-mum CMOS technology that has been simulated at 10 Gb/s. The synchronizing block exhibits the small dc power consumption of 2.09 mW for 1 V power supply and the chip size of this block is 750 mum times 615 mum.

Keywords

CMOS integrated circuits; flip-flops; low-power electronics; optical interconnections; optical links; synchronisation; CMOS technology; D flip flop; asynchronous signal; bit rate 10 Gbit/s; clock signal; electrically linked interconnections; optically linked interconnections; power 2.09 mW; signal latency evaluation; signal synchronization; signal synchronizing block; size 0.13 mum; small dc power consumption; voltage 1 V; voltage control delay cell; CMOS technology; Clocks; Delay; Energy consumption; Flip-flops; Optical interconnections; Power supplies; Signal design; Synchronization; Voltage control; Signal latency; electrical interconnection; optical interconnection; synchronizing block; voltage control delay cell (VCDC);

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Technology, 2008. ICACT 2008. 10th International Conference on

Conference_Location

Gangwon-Do

ISSN

1738-9445

Print_ISBN

978-89-5519-136-3

Type

conf

DOI

10.1109/ICACT.2008.4494217

Filename

4494217