The v2.0+EDR Bluetooth SOC architecture for multimedia

Author

Kim, Jeonghun ; Sim, Taehyeon ; Choi, Youngwhan ; Jeong, Jungwon ; Bang, Taesik ; Kim, Suki

Author_Institution

Dept. of Electron. Eng., Korea Univ., Seoul, South Korea

fYear

2006

fDate

7-11 Jan. 2006

Firstpage

195

Lastpage

196

Abstract

This paper proposes the advanced Bluetooth SOC architecture for multimedia applications. Our design includes baseband functions in compliance with Bluetooth core specification v2.0+EDR (enhanced data rate), RF transceiver, modem, SBC codec, ESIC processor, and power management block. This chip is SIP integration with the flash memory and occupies a die size of 28 mm² in CMOS 0.18 μm. The maximum current consumption of the total chip is 65 mA. The single operation voltage of the analog and the digital parts is 1.8 V.

Keywords

Bluetooth; CMOS integrated circuits; multimedia communication; system-on-chip; 1.8 V; 65 mA; Bluetooth SOC architecture; CMOS; RF transceiver; current consumption; enhanced data rate; expended instruction set computer processor; flash memory; modem; multimedia applications; power management block; subband codec; Bluetooth; Clocks; Cyclic redundancy check; Payloads; Phase change materials; Phase shift keying; Radio frequency; Random access memory; Transceivers; Universal Serial Bus;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2006. ICCE '06. 2006 Digest of Technical Papers. International Conference on

Print_ISBN

0-7803-9459-3

Type

conf

DOI

10.1109/ICCE.2006.1598377

Filename

1598377