DocumentCode :
3311382
Title :
Applications and performance analysis of a compile-time optimization approach for list scheduling algorithms on distributed memory multiprocessors
Author :
Chung, Yeh-Ching ; Ranka, Sanjay
Author_Institution :
Dept. of Inf. Eng., Feng Chia Univ., Taichung, Taiwan
fYear :
1992
fDate :
16-20 Nov 1992
Firstpage :
512
Lastpage :
521
Abstract :
The authors discuss applications of BTDH (bottom-up top-down duplication heuristic) to list scheduling algorithms (LSAs). There are two ways to use BTDH for LSAs. BTDH can be used with an LSA to form a new scheduling algorithm (LSA/BTDH), and it can be used as a pure optimization algorithm for an LSA (LSA-BTDH). BTDH has been applied with two well-known LSAs: the highest level first with estimated time (HLFET) and the earlier task first (ETF) heuristics. Simulation results show that, given a directed acyclic growth (DAG), the graph parallelism of the DAG can accurately predict the number of processors to be used such that a good scheduling length and a good resource utilization (or efficiency) can be achieved simultaneously. In terms of speedups, LSA/BTDH ⩾ LSA-BTDH ⩾ ETF ⩾ HLFET. Experimental results of scheduling FFT programs, which are written in a single program multiple data (SPMD) programming approach, on NCUBE-2 are also presented. The results confirm the simulation results and show that the speedups of LSA/BTDH and LSA-BTDH are better than the speedups of LSAs
Keywords :
directed graphs; distributed memory systems; performance evaluation; program compilers; scheduling; FFT programs; NCUBE-2; bottom-up top-down duplication heuristic; compile-time optimization; directed acyclic growth; distributed memory multiprocessors; earlier task first; graph parallelism; highest level first with estimated time; list scheduling algorithms; optimization algorithm; performance analysis; resource utilization; simulation; single program multiple data; Application software; Computational efficiency; Computational modeling; Concurrent computing; Contracts; Parallel processing; Performance analysis; Processor scheduling; Resource management; Scheduling algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Supercomputing '92., Proceedings
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-8186-2630-5
Type :
conf
DOI :
10.1109/SUPERC.1992.236653
Filename :
236653
Link To Document :
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