Title :
Deterministic BIST with partial scan
Author :
Kiefer, Gundolf ; Wunderlich, Hans-Joachim
Author_Institution :
Comput. Archit. Lab., Stuttgart Univ., Germany
Abstract :
An efficiency deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flip-flops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flip-flops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.
Keywords :
automatic testing; built-in self test; fault diagnosis; flip-flops; logic testing; minimisation; deterministic BIST; flip-flops; hardware overhead; minimum number; on-chip pattern generator; partial scan chains; pipeline-like structure; scan selection algorithm; system performance; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Electronic switching systems; Hardware; Signal generators; System performance; System testing;
Conference_Titel :
European Test Workshop 1999. Proceedings
Conference_Location :
Constance, Germany
Print_ISBN :
0-7695-0390-X
DOI :
10.1109/ETW.1999.804415
