Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators

Author

Koutsomyti, Konstantia ; Chouliaras, Vassilios A. ; Parr, Simon R. ; Nunez-Yanez, Jose Luis ; Datta, Sekharjit

Author_Institution

Loughborough Univ.

fYear

2006

fDate

7-11 Jan. 2006

Firstpage

279

Lastpage

280

Abstract

We developed parametric data-parallel and scalar instruction set extensions for accelerating the ITU-T G.723.1 and G.729.A speech coding standards. Using a novel hybrid methodology, we synthesized the custom hardware accelerators via encapsulating the C-based descriptions of the original scalar and SIMD instruction set extensions in a hybrid, SystemC- RTL hardware wrapper and introduced it into the scalar and vector extension datapaths of a next-generation configurable, extensible multi-threaded CPU. We discuss this methodology and present a VLSI implementation of a 128-bit wide configuration of the data-parallel and scalar coprocessor attached to a dual-threaded instance of this CPU

Keywords

code standards; instruction sets; multi-threading; speech coding; C-based descriptions; G.729.A speech coding standards; ITU-T G.723.1 speech coding standards; SIMD instruction set extensions; SystemC; SystemC- RTL hardware wrapper; VLSI; hardware accelerators; scalar accelerators; synthesized SIMD; Acceleration; Application specific integrated circuits; Hardware; Life estimation; Optimization methods; Reduced instruction set computing; Speech coding; Speech synthesis; Standards development; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2006. ICCE '06. 2006 Digest of Technical Papers. International Conference on

Conference_Location

Las Vegas, NV

Print_ISBN

0-7803-9459-3

Type

conf

DOI

10.1109/ICCE.2006.1598419

Filename

1598419