Title :
Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class Semi-Super Junction MOSFET
Author :
Ono, Syotaro ; Saito, Wataru ; Takashita, Masakatsu ; Kurushima, Shoichiro ; Tokano, Ken´ichi ; Yamaguchi, Masakazu
Author_Institution :
Toshiba Corp., Kawasaki
Abstract :
We report the experimental results detailed about the n-buffer layer (n-BAL: n-bottom assist layer) of 600 V-class semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (RonA) and the breakdown voltage (VB), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio TBAL-ratio and the doping concentration NBAL were varied in this work. As a result, the VB=750 V, the RonA=24.6 mOmegacm2, the maximum avalanche current density JAP=292 A/cm2 (IAP=7.6A, EAS=1.25 J/cm2), and softness factor=0.277 were obtained with the structure of TBAL-ratio=27% and NBAL=1.0x1015cm-3. The demonstration results showed that NPT (non punch through)-type design (with high TBAL-ratio and high NBAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (punch through)-type design.
Keywords :
MOSFET; integrated circuit design; semiconductor diodes; avalanche capability; current 7.6 A; design optimization; diode characteristic; n-bottom assist layer; nonpunch through-type design; semi-super junction MOSFET; softer reverse recovery characteristic; voltage 600 V; voltage 750 V; Current density; Design optimization; Doping; Facsimile; MOSFET circuits; Power MOSFET; Power semiconductor devices; Power supplies; Semiconductor diodes; Voltage;
Conference_Titel :
Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on
Conference_Location :
Jeju Island
Print_ISBN :
1-4244-1095-9
Electronic_ISBN :
1-4244-1096-7
DOI :
10.1109/ISPSD.2007.4294923