Array enhanced logical stochastic resonance in the presence of delta correlated noise

In the presence of noise floor, we investigate the logical stochastic resonance phenomenon in a parallel array consisting of bistable devices, which is driven by various cycling combinations of logic inputs. The probability of the correct logic output is calculated according to true table of logic relationships. In contrast with a single system, the significant logic response can be extracted in a wider optimal window of noise. Increasing the array size tends to expand the effective working parameter domain in which the reliable logic operation is able to occur. It is also demonstrated that the array enhanced logical stochastic resonance has a saturating effect at larger array size. The small or medium array size is good enough for one to obtain reliable logic operation. The present structure can be realized by a set of CMOS based circuits or nanoelectronic devices, and further work as the basic ingredient of general purpose hardware that has the potential for the reconfigurability.