Optimized design of hybrid CMOS and CNFET 32 nm dual-X current conveyor

Author

Imran, Ale ; Pable, S.D. ; Islam, Aminul ; Hasan, Mohd

Author_Institution

Dept. of Electron. Eng., A.M.U., Aligarh, India

fYear

2011

fDate

17-19 Dec. 2011

Firstpage

76

Lastpage

79

Abstract

There is a rapid need to explore circuit designs in the newly emerging technologies to help extend the saturating Moore´s Law. This paper presents the optimized design and performance analysis of Dual-X Current Conveyor with the Hybrid CMOS and CNFET technologies at 32nm technology node. Current Bandwidth, Input and Output Port resistances of the device and the average power dissipated are chosen as the parameters of reference for carrying out the analysis. Simulations have been carried out using HSPICE simulator at a reduced power supply of ±0.9V.

Keywords

CMOS integrated circuits; SPICE; carbon nanotube field effect transistors; current conveyors; hybrid integrated circuits; integrated circuit design; semiconductor device models; CNFET design; HSPICE simulator; Moore´s Law; circuit designs; dual-X current conveyor; hybrid CMOS design; size 32 nm; voltage 0.9 V; Bandwidth; CMOS integrated circuits; CMOS technology; CNTFETs; MOSFETs; Performance evaluation; Hybrid CMOS &CNFET DXCCII; Port Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Multimedia, Signal Processing and Communication Technologies (IMPACT), 2011 International Conference on

Conference_Location

Aligarh

Print_ISBN

978-1-4577-1105-3

Type

conf

DOI

10.1109/MSPCT.2011.6150440

Filename

6150440