An approach to the development of a Iddq testable cell library

Author

Ferrer, C. ; Mateo, D. ; Oliver, J. ; Rubio, A. ; Rullan, M.

Author_Institution

CNM, Univ. Autonoma de Barcelona, Spain

fYear

1994

fDate

17-19 Oct 1994

Firstpage

46

Lastpage

54

Abstract

Many VLSI integrated circuit processing defects can cause changes in the behaviour of the quiescent power supply current. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide range of physical defects. In this paper we present one approach to Iddq testing based on the application of BIC sensors to a cell library design methodology. The size of the sensor will depend on the length of the row as well as on the frequency of the circuit under test

Keywords

logic testing; BIC sensors; CMOS circuits; Iddq testing; VLSI integrated circuit; built-in current techniques; cell library; circuit under test; design methodology; inspection; physical defects; processing defects; quiescent power supply current; Automatic testing; Capacitors; Circuit faults; Circuit testing; Current measurement; Electrical fault detection; Frequency; Libraries; Logic testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Conference_Location

Montreal, Que.

ISSN

1550-5774

Print_ISBN

0-8186-6307-3

Type

conf

DOI

10.1109/DFTVS.1994.630013

Filename

630013