• DocumentCode
    3313027
  • Title

    A 70V UMOS Technology with Trenched LOCOS Process to Reduce Cgs

  • Author

    Wang, Hao ; Trescases, Olivier ; Xu, H. P Edward ; Ng, Wai Tung ; Fukumoto, Kenji ; Ishikawa, Akira ; Furukawa, Yuichi ; Imai, Hisaya ; Naito, Takashi ; Sato, Nobuyuki ; Sakai, Kimio ; Tamura, Satoru ; Takasuka, Kaoru

  • Author_Institution
    Univ. of Toronto, Toronto
  • fYear
    2007
  • fDate
    27-31 May 2007
  • Firstpage
    181
  • Lastpage
    184
  • Abstract
    A trenched LOCOS process has been applied to a UMOS structure to reduce the gate-to-source overlap capacitance (Cgs). A 40% reduction in Cgs is achieved comparing to conventional UMOS, and the device´s specific on- resistance Ron, sp = 60 mOmegaldrmm2 is observed. The improvement in device figure-of-merit (FOM = Ron times Qg) is about 58%.
  • Keywords
    power MOSFET; UMOS technology; device figure-of-merit; gate-to-source overlap capacitance; trench MOSFET; trenched LOCOS process; voltage 70 V; Back; Boron; Capacitance; Epitaxial layers; Etching; Fabrication; MOSFETs; Oxidation; Shoulder; Switching loss;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on
  • Conference_Location
    Jeju Island
  • Print_ISBN
    1-4244-1095-9
  • Electronic_ISBN
    1-4244-1096-7
  • Type

    conf

  • DOI
    10.1109/ISPSD.2007.4294962
  • Filename
    4294962
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3313027