Efficient critical area algorithms and their application to yield improvement and test strategies

Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a given size. The edges are used to generate fault critical areas. These are critical areas that are classified by the list of circuit nodes that are shorted by a defect of the given size falling within that area. Fault critical areas generated for a range of defect sizes can be used to produce fault probabilities between individual circuit nodes and enable device test procedures and redundancy strategies to be optimised. The algorithms have the advantage that they are not restricted to Manhatten layout and that they are computationally efficient