Title :
The effect of wire length minimization on yield
Author :
Chiluvuri, Venkat K R ; Koren, Israel ; Burns, Jeffrey L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Wire length minimization (WLM) has received significant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may still exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout patterns and the spacing among them must be considered. The trade-off between these two features is analyzed on a set of benchmark layouts in this paper
Keywords :
circuit optimisation; VLSI layout synthesis; circuit yield; compaction; wire length minimization; Circuit faults; Circuit synthesis; Compaction; Manufacturing processes; Minimization; Performance analysis; Production facilities; Routing; Very large scale integration; Wire;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-8186-6307-3
DOI :
10.1109/DFTVS.1994.630019
