DocumentCode :
3313799
Title :
Layout to Logic Defect Analysis for Hierarchical Test Generation
Author :
Jenihhin, Maksim ; Raik, Jaan ; Ubar, Raimund ; Pleskacz, Witold A. ; Rakowski, Michal
Author_Institution :
Tallinn Univ. of Technol., Tallinn
fYear :
2007
fDate :
11-13 April 2007
Firstpage :
1
Lastpage :
6
Abstract :
As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeting these defects, such as the bridging fault test pattern generators have been available for a long time. However, this paper proposes a new hierarchical approach based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logic-level test pattern generation for bridging faults. Experiments on real design layouts will show that only a fraction of all the possible pairs of nets have non-zero shorting probabilities. Furthermore, it will also be proven at the logic-level that nearly all such bridging faults can be tested by a simple and robust one-pattern logic test. The methods proposed in this paper are supported by a design flow implementing existing commercial and academic CAD software.
Keywords :
CMOS logic circuits; circuit analysis computing; electronic design automation; CAD software; CMOS circuits; hierarchical test generation; interconnect wires; logic defect analysis; logic-level test pattern generation; CMOS logic circuits; Circuit faults; Circuit testing; Data mining; Fault diagnosis; Integrated circuit interconnections; Logic testing; Semiconductor device modeling; Test pattern generators; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE
Conference_Location :
Krakow
Print_ISBN :
1-4244-1162-9
Electronic_ISBN :
1-4244-1162-9
Type :
conf
DOI :
10.1109/DDECS.2007.4295251
Filename :
4295251
Link To Document :
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