A fault-tolerant associative approach to on-line memory repair

Author

Lo, Jien-Chung

Author_Institution

Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA

fYear

1994

fDate

17-19 Oct 1994

Firstpage

168

Lastpage

176

Abstract

A fault-tolerant associative approach is proposed to be used in on-line repair for highly available memories. The memory repair mechanism is designed similar to a cache memory in its spare to main memory mapping schemes. Four spare memory mapping schemes are presented: fully associative, associative direct, associative set and associative multiple. If cache memory repair is needed, the proposed schemes can also be applied. The repair mechanism consists of a TMR content addressable memory (CAM) and an SEC/DED spare data memory. Although it is sufficient to encode the CAM with SEC code, we find that TMR version is faster in accessing time and more cost-effective. To repair a 1M×32 main memory with eight spare words, the proposed schemes use less than 0.015% of hardware redundancy

Keywords

computer maintenance; SEC code; SEC/DED spare data memory; TMR content addressable memory; associative direct scheme; associative multiple scheme; associative set scheme; cache memory; fault tolerance; fully associative scheme; hardware redundancy; on-line memory repair; spare to main memory mapping; Associative memory; CADCAM; Cache memory; Computer aided manufacturing; Error correction codes; Fault detection; Fault tolerance; Hardware; Protection; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Conference_Location

Montreal, Que.

ISSN

1550-5774

Print_ISBN

0-8186-6307-3

Type

conf

DOI

10.1109/DFTVS.1994.630027

Filename

630027