Title :
THE VLSI AREA OF HIGH RATE LINEAR FILTERS USING LOOP PIPELINING AND PARALLELISM
Author :
Bliss, William G. ; Wu, Kevin Chi-Rung
Keywords :
Arithmetic; Concurrent computing; Delay; Finite impulse response filter; IIR filters; Nonlinear filters; Parallel processing; Pipeline processing; Throughput; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1990 Conference Record Twenty-Fourth Asilomar Conference on
Print_ISBN :
0-8186-2180-X
DOI :
10.1109/ACSSC.1990.523466
