Title :
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology
Author :
Liang, Zhicheng ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Tokyo Univ., Tokyo
Abstract :
Increasing level of process variation in the sub-100 nm silicon technology is becoming an important issue. In this paper we describe an approach to estimate the impact of process variations on the static CMOS and the dual-rail PLA down to 32 nm process. This approach is built on accurate variation modeling, published data including the ITRS, Predictive Technology Models, and Monte-Carlo analysis. The analysis results show that a challenge due to insufficient noise margins is posed to the static CMOS at 32 nm, and to the dual-rail PLA from 90 nm. Then a one-side virtual ground structure is also proposed to improve the noise margins of the dual-rail PLA. The improved dual-rail PLA is shown to work down to 32 nm process with keeping an operational margin of 150 mv.
Keywords :
CMOS integrated circuits; Monte Carlo methods; integrated circuit design; logic design; nanotechnology; programmable logic arrays; CMOS technology; ITRS; Monte-Carlo analysis; device parameter variations; dual-rail PLA; noise margins analysis; predictive technology models; silicon technology; size 100 nm; size 32 nm; size 90 nm; voltage 150 mV; CMOS process; CMOS technology; Design engineering; Educational technology; Fluctuations; Integrated circuit technology; Predictive models; Programmable logic arrays; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE
Conference_Location :
Krakow
Print_ISBN :
1-4244-1162-9
Electronic_ISBN :
1-4244-1162-9
DOI :
10.1109/DDECS.2007.4295258
