Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder

Memory is a significant performance limiting factor of the multiprocessor systems especially when shared. In FPGAs, the memory amount of the device is fixed and thus, optimal memory usage is essential. This paper analyses how the fixed amount of memory should be divided between instruction memories and instruction caches for multiprocessor systems and compromised with the number of processors. The measurements are done with a SPMD (Single Program Multiple Data) multiprocessor system of up to 14 soft core processors running a MPEG-4 video encoder on FPGA. The instruction memory count is ranged between one and seven. It is shown that the traditional distributed memory architecture is outperformed by shared instruction memories with sufficient cache sizes. The number of processors is in general the most significant single factor once the sufficient cache size is reached. The best performance was obtained with only one shared instruction memory, 8 KB cache and 13 processors.