A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling

Author

Kim, Dongsoo ; Han, Gunhee

Author_Institution

Yonsei Univ., Seoul

fYear

2007

fDate

11-13 April 2007

Firstpage

1

Lastpage

3

Abstract

A low noise and low power CMOS image sensor (CIS) with pixel-level correlated double sampling (CDS) is proposed. As the pixel readout circuit using source follower is major readout noise and power consumption source in the conventional CIS structure, the proposed new structure removes the source follower and performs pixel-level CDS and comparing. The proposed CIS is integrated with 240 times 180 pixel array. A pixel fill factor is 32% and its pitch is 8.4 mum. The test chip was fabricated with CMOS 0.35-mum process and its power consumption is 18 mW with 3.3 V occupying 8.1 mm².

Keywords

CMOS image sensors; analogue-digital conversion; circuit noise; low-power electronics; readout electronics; CMOS image sensor; CMOS process; pixel readout circuit; pixel-level correlated double sampling; power 18 mW; power consumption source; readout noise; size 0.35 mum; source follower; voltage 3.3 V; CMOS image sensors; Capacitors; Circuits; Computational Intelligence Society; Energy consumption; Image sampling; Inverters; Low-frequency noise; Pixel; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE

Conference_Location

Krakow

Print_ISBN

1-4244-1162-9

Electronic_ISBN

1-4244-1162-9

Type

conf

DOI

10.1109/DDECS.2007.4295263

Filename

4295263