• DocumentCode
    3314054
  • Title

    Lightweight Multi-threaded Network Processor Core in FPGA

  • Author

    Buciak, Piotr ; Botwicz, Jakub

  • Author_Institution
    Warsaw Univ. of Technol, Warsaw
  • fYear
    2007
  • fDate
    11-13 April 2007
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    The aim of this paper is to present a simple, lightweight, multi-threaded network processor core implemented in a FPGA circuit 1. The authors prove that it is possible to design a processor core with hardware switched threads in a FPGA integrated circuit efficiently. The details of the processor core´s architecture are described. The compilation results prove, that the proposed core is able to run at a frequency of 180 MHz in a high-end FPGA device.
  • Keywords
    computer architecture; digital integrated circuits; field programmable gate arrays; integrated circuit design; logic design; microprocessor chips; FPGA integrated circuit; frequency 180 MHz; hardware switched threads; multithreaded network processor core architecture; Computer networks; Field programmable gate arrays; Frequency; Hardware; Home appliances; Manufacturing processes; Network interfaces; Process design; Throughput; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE
  • Conference_Location
    Krakow
  • Print_ISBN
    1-4244-1162-9
  • Electronic_ISBN
    1-4244-1162-9
  • Type

    conf

  • DOI
    10.1109/DDECS.2007.4295266
  • Filename
    4295266
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3314054