• DocumentCode
    3314157
  • Title

    Instance Generation for SAT-based ATPG

  • Author

    Tille, Daniel ; Fey, Görschwin ; Drechsler, Rolf

  • Author_Institution
    Bremen Univ., Bremen
  • fYear
    2007
  • fDate
    11-13 April 2007
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Recently, there is a renewed interest in Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT). This results from the availability of very powerful SAT solvers that have been developed in the last few years. Studies have shown that SAT-based ATPG tools can clearly outperform classical approaches for hard-to-test faults. While the ATPG problem has to be solved on a circuit, SAT solvers work on Conjunctive Normal Forms (CNFs). In this paper the problem to efficiently generate a SAT instance from a circuit is studied. Experimental results on large industrial circuits show the efficiency of the approach.
  • Keywords
    Boolean functions; automatic test pattern generation; fault diagnosis; fault simulation; integrated circuit testing; Boolean satisfiability; automatic test pattern generation; conjunctive normal forms; hard-to-test faults; Automatic test pattern generation; Boolean functions; Circuit faults; Circuit testing; Computer science; Encoding; Impedance; Logic; Performance evaluation; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE
  • Conference_Location
    Krakow
  • Print_ISBN
    1-4244-1162-9
  • Electronic_ISBN
    1-4244-1162-9
  • Type

    conf

  • DOI
    10.1109/DDECS.2007.4295272
  • Filename
    4295272