Manifestation of Precharge Faults in High Speed DRAM Devices

High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result in their own set of faults, and increase the complexity of already known faults. This paper describes the influence of bit line coupling on precharge faults, where the memory is rendered unable to set the proper precharge voltages at the end of each operation, which causes the memory to fail in subsequent read operations. This kind of bit line coupling effect on precharge behavior has been observed in high speed DRAMs at Qimonda. This paper gives a detailed analysis of the problem, and suggests effective tests to detect it. The paper also describes the results of an industrial test evaluation on actual DRAMs chips, performed to validate the effectiveness of the proposed tests.