• DocumentCode
    3314296
  • Title

    A general method to design and reconfigure loop-based linear arrays

  • Author

    Shi, Weiping

  • Author_Institution
    Dept. of Comput. Sci., Univ. of North Texas, Denton, TX, USA
  • fYear
    1994
  • fDate
    17-19 Oct 1994
  • Firstpage
    221
  • Lastpage
    229
  • Abstract
    Loop-based defect-tolerant design of linear arrays is easy to manufacture, test and reconfigure. Previous researchers have given ad hoc designs for specific number of neighbors and interconnection patterns. In this paper, we give general results on design and reconfiguration for any number of neighbors and interconnection patterns to achieve best cost/performance
  • Keywords
    reconfigurable architectures; defect-tolerant design; general design method; interconnection patterns; loop-based linear arrays; reconfiguration; Algorithm design and analysis; Computer aided manufacturing; Computer science; Costs; Delay; Design methodology; LAN interconnection; Switches; Testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1550-5774
  • Print_ISBN
    0-8186-6307-3
  • Type

    conf

  • DOI
    10.1109/DFTVS.1994.630033
  • Filename
    630033
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3314296