• DocumentCode
    3314346
  • Title

    A yield study of VLSI adders

  • Author

    Chen, Zhan ; Koren, Israel

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
  • fYear
    1994
  • fDate
    17-19 Oct 1994
  • Firstpage
    239
  • Lastpage
    245
  • Abstract
    Several 64-bit adders have been designed and their expected yield has been estimated. Our results show that the yield of VLSI adders can be improved by modifying the layout of the original design and/or by choosing a different layout and circuit structure. In certain situations, these approaches can improve the yield by 10% to 17%
  • Keywords
    adders; 64 bit; VLSI adders; carry-lookahead adder; carry-skip adder; hybrid adder; layout modification; yield study; Adders; Circuits; Conferences; Contracts; Delay; Floating-point arithmetic; Libraries; Process design; Very large scale integration; Yield estimation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1550-5774
  • Print_ISBN
    0-8186-6307-3
  • Type

    conf

  • DOI
    10.1109/DFTVS.1994.630035
  • Filename
    630035
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3314346