• DocumentCode
    3314362
  • Title

    An architecture of multi-DSP system and development environment for two-dimensional digital signal processing

  • Author

    Nakajo, H. ; Yoshikawa, K. ; Hinamoto, Takao ; Maekawa, S.

  • Author_Institution
    Dept. of Comput. & Syst. Eng., Kobe Univ., Japan
  • fYear
    1992
  • fDate
    17-19 Sep 1992
  • Firstpage
    193
  • Lastpage
    196
  • Abstract
    A multi-DSP (digital signal processor) system which attempts to investigate algorithms for real-time digital signal processing is presented. A parallel digital filtering algorithm and a development environment are also described. It is found that the multi-DSP system has significantly higher computation performance than an engineering workstation. However, since the multi-DSP system requires significant data transfer capability, to achieve total higher performance, the bandwidth of the communication network between the workstation and the multi-DSP system must be improved
  • Keywords
    development systems; digital signal processing chips; parallel algorithms; parallel architectures; real-time systems; signal processing; two-dimensional digital filters; 2D digital signal processing; communication network bandwidth; computation performance; data transfer capability; development environment; multi-DSP system; parallel digital filtering algorithm; real-time system; system architecture; two-dimensional digital signal processing; Bandwidth; Communication networks; Computer architecture; Digital signal processing; Digital signal processors; Filtering algorithms; High performance computing; Real time systems; Signal processing algorithms; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Systems Engineering, 1992., IEEE International Conference on
  • Conference_Location
    Kobe
  • Print_ISBN
    0-7803-0734-8
  • Type

    conf

  • DOI
    10.1109/ICSYSE.1992.236910
  • Filename
    236910