Test generation for stuck-at and gate-delay faults in sequential circuits: a mixed functional/structural method

Author

Fummi, F. ; Sciuto, D. ; Serra, M.

Author_Institution

Dipartimento di Elettronica, Politecnico di Milano, Italy

fYear

1994

fDate

17-19 Oct 1994

Firstpage

254

Lastpage

262

Abstract

This paper presents a mixed approach for sequential circuit test pattern generation employing the accuracy of structural algorithms and the speed of a pattern generator working at the functional level. The new strategy selects from the State Transition Graph of a Finite State Machine the appropriate edges that allow a functional test pattern generator (FSMTest) to build test sequences covering 100% of the detectable single stuck-at and gate-delay faults. Experiments and comparisons are presented to justify the proposed test strategy

Keywords

logic testing; DelayFAN; FSMTest; STGFAN; TPG; finite state machine; gate-delay faults; mixed functional/structural method; sequential circuits; state transition graph; structural algorithms; stuck-at faults; test pattern generation; test sequences; Automata; Circuit faults; Circuit synthesis; Circuit testing; Computer science; Delay; Process design; Sequential analysis; Sequential circuits; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Conference_Location

Montreal, Que.

ISSN

1550-5774

Print_ISBN

0-8186-6307-3

Type

conf

DOI

10.1109/DFTVS.1994.630037

Filename

630037