Alternative approaches to fault detection in FSMs

This paper addresses the detection of permanent or transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. On-line test devices are automatically generated by a specific synthesis tool (ASYL-SdF), avoiding design time overhead. Two approaches based on control-flow checking methods are available to the designer and it is shown that each of these approaches leads, in some cases, to the cheapest implementation. In particular, noticeable gains can be obtained compared with the classical approach based on duplication